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MAT F OR D IN 6D TE Data Sheet PDA EL755 OR U
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EL7556B
October 5, 2001 FN7292
Integrated Adjustable 6 Amp Synchronous Switcher
The EL7556B is an adjustable synchronous DC:DC switching regulator optimized for a 5V input and 1.0V-3.8V output. By combining integrated NMOS power FETs with a fused-lead package, the EL7556B can supply up to 6A continuous output current without the use of external power devices or discrete heat sinks, thereby minimizing design effort and overall system cost. On-chip resistorless current sensing is used to achieve stable, highly efficient, current-mode control. The EL7556B also incorporates the VCC2DET function to directly interface with the Intel P54 and P55 microprocessors. Depending on the state of VCC2DET, the output voltage is internally preset to 3.5V or a user-adjustable voltage using two external resistors. In both internal and external feedback modes the active-high PWRGD output indicates when the regulator output is within 10% of the programmed voltage. An onboard sensor monitors die temperature (OT) for overtemperature conditions and can be connected directly to OUTEN to provide automatic thermal shutdown. Adjustable oscillator frequency and slope compensation allow added flexibility in overall system design. The EL7556B is available in a 28-pin SO package and is specified for operation over the full -40C to +85C temperature range.
Features
* EL7556/EL7556A Pin-compatible * Improved temperature and voltage ranges * 6A continuous load current * Precision internal 1% reference * 1.0V to 3.8V output voltage * Internal power MOSFETs * >90% efficiency * Synchronous switching * Adjustable slope compensation * Over-temperature indicator * Pulse-by-pulse current limiting * Operates up to 1MHz * 1.5% typical output accuracy * Adjustable oscillator with sync * Remote enable/disable * Intel P54- and P55-compatible * VCC2DET interface * Internal soft-start
Applications
* PC motherboards * Local high power CPU supplies * 5V to 1.0V DC:DC conversion * Portable electronics/instruments
Pinout
EL7556B (28-PIN SO) TOP VIEW
R4 R3 100 150
VIN
D3
* P54 and P55 regulators * GTL + Bus power supply
1 C4 0.1F 2 C7 39pF 3 C8 R5 5 5.1 6 7 C9 C12 1F C3 1F 8 9 10 11 12 Connect to VSSP for external feedback 13 14 220pF 4
FB1 CREF CSLOPE COSC VDD VIN VSSP VIN VSSP VSSP VSSP VSSP
FB2 28 CP C2V VSS 27 R1 26 20 25 R6 VHI 24 C6 LX LX LX LX VSSP VSSP TEST 23 0.1F 22 21 20 19 18 17 L1 2.5H C10 1mF 39.2 D1 C11 0.22F C5 1F D2 D4* (Optional)
Ordering Information
VOUT = 1V*(1+R3/R4)
VIN
660F
PART NUMBER EL7556BCM EL7556BCM-T13
PACKAGE 28-Pin SO 28-Pin SO
TAPE & REEL 13"
PKG. NO. MDP0027 MDP0027
VCC2DET 16 PWRGD OUTEN OT 15
C12 - 1F C3, C4, C5, C6, C7 C8 - ceramic C5, C11 - ceramic or tantalum C9 - Sprague 293D337X96R3 2X330F C10 - Sprague 293D337X96R3 3X330F L1 - Pulse Engineering, PE-53681 D1-D4: BAT54S fast diode D4 Required for EL7556ACM Only
Manufactured under U.S. Patents No. 5,723,974 and No. 5,793,126
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
EL7556B
Absolute Maximum Ratings (TA = 25C)
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Supply (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0V Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Output Pins . . . . . . . . . . . . . . . -0.3V below GND, +0.3V above VDD Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 135C Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9A
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER GENERAL IDD IDDOFF IVIN VOUT1 VOUT2 VOUTLINE VOUTLOAD RSHORT II MAX VOUTTC TOT THYS VPWRGD VDDOFF VDDON VHYS MSS DMAX
VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
VDD Supply Current VDD Standby Current VIN No Load Current Output Initial Accuracy Output Initial Accuracy Output line Regulation Output Load Regulation Short Circuit Load Resistance Current Limit Output Tempco Over Temperature Threshold Over Temperature Hysteresis Power Good Threshold Relative to Programmed Output Voltage Minimum VDD for Shutdown Maximum VDD for Startup Input Hysteresis Soft start slope Maximum duty cycle
OUTEN = 4V, FOSC = 120kHz OUTEN = 0 OUTEN = 0 VCC2DET = 4V, IL = 3A (See Fig. 1) VCC2DET = 0V, IL = 3A R3 = 150, R4 = 100 VDD = 5V, 10% 0A11 0.1 3 3.500 2.500
25
mA mA
5 3.550 2.550 1 1
mA V V % % m A % C C
100 9
-40C1 135 40
VCC2SEL = 4V, VOUT = 3.50V
6 3.15
10
14
% V
4.15 VHYS = VDDON-VDDOFF 0.5 7 96
V V V/mS %
CONTROLLER - INPUTS IPUP ICSLOPE IFB1 ROT VIH VIL VOH PWGD VOL PWGD VCC2DET, OUTEN Pull Up Current CSLOPE Charging Current FB1 Input Pull Up Current Over Temperature Pull Up Resistance VCC2DET, OUTEN Input High VCC2DET, OUTEN Input Low Powergood Drive High Powergood Drive Low ILOAD = 1mA ILOAD = -1mA 3.5 1.0 OT = 0V 30 4 0.8 VCC2DET, OUTEN = 0 10 23 14 28.5 2 40 50 18 34 A A A k V V V V
2
EL7556B
Electrical Specifications
PARAMETER VDD = VIN = 5V, COSC = 1nF, CSLOPE = 470pF, TA = 25C unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
CONTROLLER - REFERENCE VREF VREFTC VREFLOAD Reference Accuracy Reference Voltage Tempco Reference Load Regulation 0CONTROLLER - DOUBLER VC2V Voltage Doubler Output VDD = 5V, ILOAD = 10mA 7.5 8.1 8.7 V
CONTROLLER - OSCILLATOR FRAMP IOSC CHG IOSC DIS FOSC tSYNC POWER - FET ILEAK RDSON RDSONTC tBRM tLEB LX Output Leakage to VSS Composite FET Resistance RDSON Tempco FET break before make delay High side FET minimum on time (LEB) LX = 0V 18 0.1 10 140 100 30 A m m/C ns ns Oscillator Ramp Amplitude Oscillator Charge Current Oscillator Discharge Current Oscillator initial accuracy Minimum oscillator sync width 0.2V3
EL7556B Typical Performance Curves
Efficiency vs ILOAD (VOUT =3.5V) VDD=VIN=5.0V (10%) 96 94 92 Efficiency (%) VDD=5V Efficiency (%) 90 88 86 84 82 80 0.5 75 TA=25C 1.5 2.5 3.5 IOUT (A) 4.5 5.5 6.5 70 0.5 1.5 2.5 3.5 IOUT (A) 4.5 5.5 6.0 VDD=5.5V 90 VCC=2.5V 85 80 VCC=1V VDD=4.5V 95 VCC=3.5V 100 Efficiency vs ILOAD (VDD=5.0V)
Line Regulation (CSLOPE=100pF) 3.54 3.53 3.52 3.51 VOUT (V) 3.50 3.49 3.48 3.47 3.46 4.5 IOUT=6A TA=25C 5.0 VIN (V) 5.5 IOUT=3A IOUT=0.5A VOUT (V) 3.54 3.53 3.52 3.51 3.50 3.49 3.48 3.47 3.46
Load Regulation (CSLOPE=100pF)
VIN=5V VIN=5.5V
VIN=4.5V TA=25C 0.5 3.0 IOUT (A) 6.0
Line Regulation vs CSLOPE (IOUT=3A) VDD=VIN=5.0V 10% 0.8 0.7 0.6 VOUT () (%) 0.5 0.4 0.3 0.2 0.1 0.0 50 75 100 125 150 175 CSLOPE (pF) 0.1 VOUT=1A 0.0 VOUT=3.5A VOUT=2.5A VOUT () (%) 0.4 0.3 0.2 TA=25C 0.5 0.6
Load Regulation vs CSLOPE (VIN=5.0V) IOUT=3A, +3A, -2.5A TA=25C VOUT=3.5A VOUT=2.5A
VOUT=1A
50
75
100
125
150
175
CSLOPE (pF)
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EL7556B Typical Performance Curves
Line Regulation vs CSLOPE VIN=VDD=5.0V 10% 0.8 0.7 0.6 VOUT () (%) 0.5 0.4 0.3 0.2 0.1 0.0 50 IOUT=0.5A IOUT=6A VOUT () (%) TA=25C 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 50 VIN=5V VIN=5.5V VIN=4.5V TA=25C
(Continued)
Load Regulation vs CSLOPE IOUT=3A, +3A, -2.5A
75
100
125
150
175
75
100
125
150
175
CSLOPE (pF)
CSLOPE (pF)
VOUT vs CSLOPE (VIN=5.0V, ILOAD=0.5A) 1.5 1.0 1.0 0.5 Deviation in VOUT (%) VOUT () (%) 0.0 -0.5 -1.0 -1.5 -2.0 -1.0 -2.5 -3.0 50 TA=25C 75 100 125 150 175 VOUT=3.5V VOUT=1V VOUT=2.5V 1.5
VOUT Variation vs Programmed Output Voltage [VIDEAL=(1+R3/R4)] TA=25C
C
0.5
C
OS C=
SL OP E =1
0.0
00 pF 22 0p F
-0.5
Loop Gain Induced Error -1.5 1.0 1.5 2.0 2.5 VIDEAL (V) 3.0 3.5 4.0
CSLOPE (pF)
FOSC vs COSC 10000 TA=25C 1000 FOSC (kHz) FOSC (kHz) 520 510 500 490 480 470 460 1 10 450 100 COSC (pF) 1k 100k
FOSC vs Temperature
VDD=4.5V
100
VDD=5.5V
10
VDD=5V
0
20
40
60
80
100
120
140
Temperature (C)
5
EL7556B Typical Performance Curves
I(VDD) + I(VIN) vs FOSC 60 TA=25C OUTEN=VDD 16 14 12 40 IVIN (mA) IQ (mA) VDD=5V VDD=4.5V 10 8 6 20 4 10 Discontinuous Mode 0 200 400 600 FOSC (kHz) Continuous Mode 800 1000 2 VDD=4.5V VDD=5V TA=25C OUTEN=VDD VDD=5.5V
(Continued)
I(VIN) vs FOSC
50
VDD=5.5V
30
Discontinuous Mode 400 600 FOSC (kHz)
Continuous Mode 800 1000
0 200
I(VDD) vs FOSC 50 45 40 35 IDD (mA) 30 25 20 15 10 5 0 200 VDD=4.5V VDD=5V VDD=5.5V IDD (mA) + IVIN TA=25C OUTEN=VDD 2.0
IDD + IVIN vs FOSC
VDD=5.5V
1.5 VDD=4.5V
VDD=5V
400
600 FOSC (kHz)
800
1000
1.0 10
100 FOSC (kHz)
1000
Power On Reset 40 TA=25C OUTEN=VDD 30 FOSC=500k 2.3 2.1 1.9 1.7 20 VOUT (V) IQ (mA) 1.5 1.3 10 1.1
Minimum Output Voltage vs FOSC
TJ=120C
VDD=5.5V
VDD=5V
VDD=4.5V 0.9 0 2.5 0.7 3.0 3.5 VDD(V) 4.0 4.5 5.0 FOSC (kHz)
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EL7556B Typical Performance Curves
JA vs Cu Area 41 39 37 JA (C/W) 35 33 31 29 27 25 0.00 Board with Inductor 8.0 7.5 7.0 6.5 ILOAD (A) 6.0 5.5 5.0 4.5 4.0 25 Still Air 100 LFPM
(Continued)
Maximum ILOAD vs Temperature 7556 Demo Board (31C/W)
Board with no Components
OUTEN connected to OT 30 35 40 45 50 55 60 65 70
1.00
2.00
3.00
4.00
5.00
6.00
Bare Cu Area (in2)
TA (C)
RDSON vs Temperature 38 36 34 RDSON (m ) 32 30 28 26 24 22 20 0 25 50 75 100 125 Temperature (C)
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EL7556B Pin Descriptions
I = INPUT, O = OUTPUT, S = SUPPLY PIN NUMBER 1 PIN NAME FB1 PIN TYPE I FUNCTION Voltage feedback pin for the buck regulator. Active when VCC2DET is logic low. Normally connected to external resistor divider between VOUT and GND. A 2A pull-up current forces VOUT to VSS in the event that FB1is floating and VCC2DET is inadvertently connected to GND. Bandgap reference bypass capacitor. Typically 0.1F to VSS. Slope compensation capacitor. Ramp width corresponds to LX duty cycle. CSLOPE to COSC ratio is normally 1:1.5. Oscillator timing capacitor. FOSC(Hz) can be approximated by: FOSC(Hz) = 0.0001/COSC. COSC in Farads. Power Supply for PWM control circuitry. Normally the same potential as VIN. Power supply for the buck regulator. Connected to the drain of the high-side NMOS FET. Ground return for the buck regulator. Connected to the source of the low-side synchronous NMOS FET. Same as pin 6. Same as pin 7. Same as pin 7. Same as pin 7. Same as pin 7. VCC2DET interface logic input. When driven to logic 1 VOUT = 3.500V. When driven to logic 0 the PWM uses FB1 to determine VOUT: VOUT = 1.0V*(1+R3/R4). The switching regulator output is enabled when logic 1. The reference voltage output operates whenever the power supply is qualified (VDD>VPOR) regardless of the state of this pin. Over temperature indicator. Normally high. Pulls low when die temperature exceeds 135C, returns to the high state when die temperature has cooled to 100C. Power good window comparator output. Logic 1 when regulator output is within 10% of programmed voltage. Test pin. Must be connected to VSSP in normal operation. Same as pin 7. Same as pin 7. Inductor drive pin. High current switching output whose average voltage equals the regulator output voltage. Same as pin 20. Same as pin 20. Same as pin 20. Gate drive to high-side driver. Bootstrapped from LX with a 0.1F capacitor. Ground return for the control circuitry. Connected to voltage doubler output. Supplies gate drive to the low-side driver. Drives the negative side of charge pump capacitor at one-half the oscillator frequency FOSC. Voltage feedback pin. Active when VCC2DET is logic 1. Internally preset to VOUT = 3.5V.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
CREF CSLOPE COSC VDD VIN VSSP VIN VSSP VSSP VSSP VSSP VCC2DET OUTEN OT PWRGD TEST VSSP VSSP LX LX LX LX VHI VSS C2V CP FB2
I I I S S S S S S S S I I O O I S S O O O O I S I O I
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EL7556B Block Diagram
FB1, Pin1 FB2, Pin 28 2-1 MUX + + VCCDET, Pin 13 CSLOPE, Pin 3 + Current Sense VDD and VIN, Pin 5,6,8 V2X PWRGD, Pin 16 CP, Pin 27 C2V, Pin 26 VHI, Pin 24
CREF, Pin 27 1.26V + OUTEN, Pin 14 Current Limit
LEB TDELAY
Q + 4V VDD RSS UVLO VDD + COSC, Pin 4 + R Over Temp Sensor VSS, Pin 25 OT, Pin 15 + CSS FF R S VSSP, Pin 9-12, 18-19 + PWM R Q S LX, Pin 20-23
S
Zero Cross Detect
Applications Information
Circuit Description General
The EL7556B is a fixed frequency, current mode controlled DC:DC converter with integrated N-channel power MOSFETs and a high precision reference. The device incorporates all of the active circuitry required to implement a cost effective, user-programmable 6A synchronous buck converter suitable for use in CPU power supplies. By combining fused-lead packaging technology with an efficient synchronous switching architecture, high power outputs (21W) can be realized without the use of discrete external heat sinks.
6. Temperature Sensor 7. Power Good and Power On Reset
PWM Controller
The EL7556B regulates output voltage through the use of current-mode controlled pulse width modulation. The three main elements in a PWM controller are the feedback loop and reference, a pulse width modulator whose duty cycle is controlled by the feedback error signal, and a filter which averages the logic level modulator output. In a step-down (buck) converter, the feedback loop forces the time-averaged output of the modulator to equal the desired output voltage. Unlike pure voltage-mode control systems current-mode control utilizes dual feedback loops to provide both output voltage and inductor current information to the controller. The voltage loop minimizes DC and transient errors in the output voltage by adjusting the PWM duty-cycle in response to changes in line or load conditions. Since the output voltage is equal to the time-average of the modulator output the relatively large LC time constants found in power supply applications generally results in low bandwidth and poor transient response. By directly monitoring changes in inductor current via a series sense resistor the controller's response time is not entirely limited by the output LC filter
Theory of Operation
The EL7556B is composed of 7 major blocks: 1. PWM Controller 2. Output Voltage Mode Select 3. NMOS Power FETS and Drive Circuitry 4. Bandgap Reference 5. Oscillator
9
-
EL7556B
and can react more quickly to changes in line or load conditions. This feed-forward characteristic also simplifies AC loop compensation since it adds a zero to the overall loop response. Through proper selection of the currentfeedback to voltage-feedback ratio, the overall loop response will approach a one pole system. The resulting system offers several advantages over traditional voltage control systems, including simpler loop compensation, pulse by pulse current limiting, rapid response to line variation and good load step response. The heart of the controller is a triple-input direct summing comparator which sums voltage feedback, current feedback and slope compensating ramp signals together. Slope compensation is required to prevent system instability which occurs in current-mode topologies operating at duty-cycles greater than 50% and is also used to define the open-loop gain of the overall system. The compensation ramp amplitude is user adjustable and is set using a single external capacitor (CSLOPE). Each comparator input is weighted and determines the load and line regulation characteristics of the system. Current feedback is measured by sensing the inductor current flowing through the high-side switch whenever it is conducting. At the beginning of each oscillator period the high-side NMOS switch is turned on and CSLOPE ramps positively from its reset state (VREF potential). The comparator inputs are gated off for a minimum period of time (LEB) after the high-side switch is turned on to allow the system to settle. The Leading Edge Blanking (LEB) period prevents the detection of erroneous voltages at the comparator inputs due to switching noise. When programming low regulator output voltages the LEB delay will limit the maximum operating frequency of the circuit since the LEB will result in a minimum duty-cycle regardless of the PWM error voltage. This relationship is shown in the performance curves. If the inductor current exceeds the maximum current limit (ILMAX), a secondary over-current comparator will terminate the high-side switch. If ILMAX has not been reached, the regulator output voltage is then compared to the reference voltage VREF. The resultant error voltage is summed with the current feedback and slope compensation ramp. The high-side switch remains on until all three comparator inputs have summed to zero, at which time the high-side switch is turned off and the low-side switch is turned on. In order to eliminate cross-conduction of the high-side and low-side switches a 10ns break-beforemake delay is incorporated in the switch driver circuitry. In the continuous mode of operation the low-side switch will remain on until the end of the oscillator period. In order to improve the low current efficiency of the EL7556B, a zerocrossing comparator senses when the inductor transitions through zero. Turning off the low-side switch at zero inductor current prevents forward conduction through the internal clamping diodes (LX to VSSP) when the low-side switch turns off, reducing power dissipation. The output enable (OUTEN) input allows the regulator output to be disabled by an external logic control signal.
Output Voltage Mode Select
The VCC2DET multiplexes the FB1 and FB2 pins to the PWM controller. A logic 1 on VCC2DET selects the FB2 input and forces the output voltage to the internally programmed value of 3.50V. A logic zero on VCC2DET selects FB1 and allows the output to be programmed from 1.0 to 3.8V. In general:
R 3 V OUT = 1V x 1 + ------ x Volt R 4
However, due to the relatively low open loop gain of the system, gain errors will occur as the output voltage and loopgain are changed. This is shown in the performance curves. (The output voltage is factory trimmed to minimize error at a 2.50V output). A 2uA pull-up current from FB1 to VIN forces VOUT to GND in the event that FB1 is not used and the VCC2DET is inadvertently toggled between the internal and external feedback mode of operation.
NMOS Power FETs and Drive Circuitry
The EL7556B integrates low resistance (25m) NMOS FETs to achieve high efficiency at 6A. Gate drive for both the high-side and low-side switches is derived through a charge pump consisting of the CP pin and external components D1D3 and C5-C6. The CP output is a low resistance inverter driven at one-half the oscillator frequency. This is used in conjunction with D2-D3 to generate a 7.5V (typical) voltage on the C2V pin which provides gate drive to the low-side NMOS switch and associated level shifter. In order to use an NMOS switch for the high-side drive it is necessary to drive the gate voltage above the source voltage (LX). This is accomplished by boot-strapping the VHI pin above the C2V voltage with capacitor C6 and diode D1. When the low-side switch is turned on the LX voltage is close to GND potential and capacitor C6 is charged through diodes D1-D3 to approximately 6.9V. At the beginning of the next cycle the high side switch turns on and the LX pin begins to rise from GND to VDD potential. As the LX pin rises the positive plate of capacitor C6 follows and eventually reaches a value of approximately 11.2V, for VDD=5V. This voltage is then level shifted and used to drive the gate of the high-side FET, via the VHI pin.
Reference
A 1% temperature compensated band gap reference is integrated in the EL7556B. The external CREF capacitor acts as the dominant pole of the amplifier and can be increased in size to maximize transient noise rejection. A value of 0.1uF is recommended.
Oscillator
The system clock is generated by an internal relaxation oscillator with a maximum duty-cycle of approximately 96%.
10
EL7556B
Operating frequency can be adjusted through the COSC pin or can be driven by an external clock source. If the oscillator is driven by an external source, care must be taken in the selection of CSLOPE. Since the COSC and CSLOPE values determine the open loop gain of the system, changes to COSC require corresponding changes to CSLOPE in order to maintain a constant gain ratio. The recommended ratio of COSC to CSLOPE is 1.5:1 package is shown in the Performance Curves section of this data sheet. It can be readily seen that the thermal resistance for this package approaches an asymptotic value of approximately 31C/W without any airflow. Additional information can be found in Application Note #8 (Measuring the Thermal Resistance of Power Surface-Mount Packages). If the thermal shutdown pin is connected to OUTEN the IC will enter thermal shutdown when the maximum junction temperature is reached. For a thermal shutdown of 135C and power dissipation of 2.2W the ambient temperature is limited to a maximum value of 67C (typical). The ambient temperature range can be extended with the application of air flow. For example, the addition of 100LFM reduces the thermal resistance by approximately 15% and can extend the operating ambient to 77C (typical). Since the thermal performance of the IC is heavily dependent on the board layout, the system designer should exercise care during the design phase to ensure that the IC will operate under the worst-case environmental conditions.
Temperature Sensor
An internal temperature sensor continuously monitors die temperature. In the event that die temperature exceeds the thermal trip-point, the OT pin will output a logic 0. The upper and lower trip points are set to 135C and 100C respectively. To enable thermal shutdown this pin should be tied directly to OUTEN. Use of this feature is recommended during normal operation.
Power Good and Power On Reset
During power up the output regulator will be disabled until VIN reaches a value of approximately 4.0V. Approximately 500mV of hysteresis is present to eliminate noise induced oscillations. Under-voltage and over-voltage conditions on the regulator output are detected through an internal window comparator. A logic 1 on the PWRGD output indicates that regulated output voltage is within 10% of the nominally programmed output voltage. Although small, the typical values of the PWRGD threshold will vary with changes to external feedback (and resultant loop gain) of the system. This dependence is shown in the typical performance curves.
Thermal Management
The EL7556B utilizes "fused lead" packaging technology in conjunction with the system board layout to achieve a lower thermal resistance than typically found in standard 28-pin SO packages. By fusing (or connecting) multiple external leads to the die substrate within the package, a very conductive heat path to the outside of the package is created. This conductive heat path MUST then be connected to a heat sinking area on the PCB in order to dissipate heat out and away from the device. The conductive paths for the EL7556B package are the fused leads: # 7, 9, 10, 11, 12, 18, and 19. If a sufficient amount of PCB metal area is connected to the fused package leads, a junction-to-ambient thermal resistance of approximately 31C/W can be achieved (compared to 78C/W for a standard SO28 package). The general relationship between PCB heatsinking metal area and the thermal resistance for this All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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